I. Field
The present disclosure generally relates to a Viterbi pack instruction. More particularly, the disclosure relates to a Viterbi pack instruction for packing bits from multiple predicate registers into a single destination register.
II. Description of Related Art
A Viterbi algorithm is an algorithm useful in communications. It may be used to decode convolutional codes used in wireless communications systems. Such codes are used in many forms of wireless communications, such as, for example only, code division multiple access (CDMA), CDMA2000, wideband code division multiple access (WCDMA), time division synchronous code division multiple access (TD-SCDMA), and global system for mobile communications (GSM). A Viterbi algorithm may also be used as an error-correction scheme, in 802.11 wireless local access networks (WLANs), in speech recognition and for many other purposes.
With a Viterbi algorithm, one finds the most likely sequence of hidden states (sometimes called the Viterbi path), in a trellis of states where there are multiple states with multiple paths that lead to each state. To determine which transition between states is most likely (sometimes called a survivor path), one may compare the likelihood of different transitions. A survivor path can be determined for each relevant state transition period across the trellis. In a Viterbi decoder, e.g., a traceback is later performed along the survivor paths to generate the output bits.
When executing a Viterbi algorithm it is common to generate and compare path metrics representing the likelihood of different transitions. A flag bit can represent the output of such a comparison. This output may be stored in memory, e.g., to be used later when performing the traceback. Having the results of several compares written into memory from separate registers takes up more memory.
For example, in a 3G wireless communications system, such as WCDMA and CDMA2000, if each flag representing the output of a comparison of two path metrics were stored in a separate byte of memory, it would take 268×256 bytes=68 kbytes of memory. However, if these bits could be stored as bits and not as bytes, it would only take 268×256/8=8 kbytes of memory.
Speed is affected by more save operations being required. This may lead to more possible cache misses. Additionally, if the flags are not saved in a natural order, it can take more cycles to perform a traceback.
Because the Viterbi algorithm is critical to, for instance, decoding the convolutional codes used in many wireless communications systems, the speed of execution of the algorithm directly affects the performance of, for example, a wireless communications system.
Accordingly, it would be advantageous to provide a Viterbi pack instruction that packs the bits within two or more predicate registers into a single destination register to speed up processing time and save memory space.